The background of the invention relates to aspects of xerography as well as micro-assembly techniques used for fabricating microstructures and microdevices, generally referred to herein as “micro-assemblies.”
The invention described below utilizes xerographic techniques as well as micro-assembly fabrication techniques. Accordingly, background information on xerography and micro-assembly fabrication techniques is provided below.
Xerography
In xerography (also known as electrophotography, electrostatographic printing, and colloquially as “photocopying”), a uniform electrostatic charge is placed upon a photoreceptor surface. The charged surface is then exposed to a light image of an original object to selectively dissipate the charge to form a latent electrostatic image of the original. The image is developed by depositing finely divided and charged particles of toner upon the photoreceptor surface. The charged toner is electrostatically attracted to the electrostatic image to create a visible replica of the original. The developed image is then transferred from the photoreceptor surface to a final substrate (e.g., paper). The toner image is then fixed (“fused”) to the substrate to form a permanent replica (“photocopy”) of the original object.
Micro-Assembly Fabrication
There are several different approaches to fabricating micro-assemblies. One approach, which is used to fabricate MEMS micro-assemblies, is referred to as “micromachining.” Micromachining utilizes standard semiconductor fabrication techniques (e.g., photolithographic patterning, isotropic/anisotropic etching, planarization, etc.). For example, digital light processors (DLPs) can be readily formed using surface-type micromachining, while pressure sensors and ink-jet printer heads typically use bulk micromachining. Other techniques, such as laser micromachining, wafer bonding, etc., may be combined with standard semiconductor fabrication techniques to enable the fabrication of advanced micro-assemblies, and in particular micro-electromechanical systems (MEMS), via micromachining.
Another technique used to fabricate micro-assemblies involves micro-assembling. Micro-assembling involves arranging very small (e.g., micron-scale) objects with a high degree of precision. One micro-assembling technique is referred to in the art as fluidic self-assembly (FSA). In FSA, devices (“function blocks”) ranging in size from 10 microns to several hundred microns and having given shapes are suspended into a liquid to form a slurry. The slurry is poured over the surface of a substrate having recessed portions therein. The recessed portions are sized to match the function blocks. In this manner, the function blocks that have been dispersed in the liquid self-align and engage the recessed portions and become integral with the substrate. Examples of FSA technology are disclosed in U.S. Pat. Nos. 5,545,291, 5,783,856, 5,824,186 and 5,904,545.
Other Micro-Assembly Fabrication Approaches
Other approaches for fabricating individual electronic components (or generally microstructures) and assembling such structures onto a substrate have been proposed. One such approach is described by Yando in U.S. Pat. No. 3,439,416. Yando describes components or structures placed, trapped, or vibrated on an array of magnets. The magnets include magnetized layers alternating with non-magnetized layers to form a laminated structure. Components are matched onto the array of magnets forming an assembly thereof. However, severe limitations exist on the shape, size, and distribution of the components. For example, the component width must match the spacing of the magnetic layers, and the distribution of components is constrained by the parallel lamination geometry. In addition, self-alignment of the components requires the presence of the laminated structure. Furthermore, the structures disclosed by Yando typically possess millimeter-sized dimensions and are therefore generally incompatible with micron-sized integrated circuit structures.
Another fabrication approach is described in U.S. Pat. No. 5,034,802 to Liebes et al., and involves mating physical features between a packaged surface mount device and substrate. The assembly process described requires a human or robotics arm to physically pick, align, and attach a centimeter-sized packaged surface mount device onto a substrate. Such a process is limiting because of the need for the human or robotics arm. The human or robotics arm assembles each packaged device onto the substrate one-by-one and not simultaneously, thereby limiting the efficiency and effectiveness of the operation. Moreover, the method uses centimeter-sized devices (or packed surface mount integrated circuits), and has little applicability to the assembly of micron-sized objects.
Another approach described in U.S. Pat. No. 4,542,397 to Biegelsen et al., involves a method of placing parallelogram-shaped structures onto a substrate by mechanical vibration. Alternatively, the method employs pulsating air through apertures in the support surface (or substrate). A limitation to the method is that it requires an apparatus capable of vibrating the structures, or an apparatus for pulsating air through the apertures. Moreover, the method described relies upon centimeter-sized dies and has little applicability to the assembly of micron-sized objects.
A further approach is described in U.S. Pat. No. 4,194,668 to Akyurek, which discloses an apparatus for aligning and soldering electrode pedestals onto solderable ohmic anode contacts. The anode contacts are portions of individual semiconductor chips located on a wafer. Assembling the structures requires techniques of sprinkling pedestals onto a mask and then electromagnetic shaking of the pedestals for alignment. The method is limited because of the need for a shaking apparatus for the electromagnetic shaking step. In addition, the method also requires a feed surface gently sloping to the mask for transferring electronic pedestals onto the mask. Moreover, the method is solely in context to electrode pedestals and silicon wafers, thereby limiting the use of such method to these structures.
Still another approach is described U.S. Pat. No. 5,355,577 to Cohn, which discloses assembling integrated circuits onto a substrate through electrostatic forces. The electrostatic forces vibrate particles into a state of minimum potential energy. A limitation with the method includes having to provide an apparatus capable of vibrating particles with electrostatic forces. Moreover, the method of Cohn tends to damage the integrated circuits by mechanically vibrating them against each other. Accordingly the method typically becomes incompatible with a state-of-art microstructures.
U.S. Pat. No. 6,796,867 to George et al., discloses a web fabrication process for manufacturing light:emitting displays as part of a high-speed, continuous in-line process. In an embodiment of the George invention, an electrostatic sheet transfer (EST) process is used to place microcomponents in corresponding sockets. In the context of the George invention, the microcomponents are light-emitting devices. The light-emitting devices are charged with one type of charge and are distributed over the oppositely charge substrate. The microcomponents adhere to the sockets because of the charge difference. Those microcomponents that do not form an electrostatic bond with corresponding sockets are removed (e.g., shaken or blown) from the substrate surface. While the process of the George patent is generally able to place microcomponents in the form of light-emitting devices into sockets for the particular application of forming a light panel, it has a number of shortcomings that prevent it from being more generally applicable to forming micro-assemblies by manipulating and assembling micro-objects. In particular, the George process lacks the ability to orient the micro-objects in specific directions. Further, the method is not particularly amenable to efficiently assembling a micro-assembly that utilizes a number of different types of micro-objects.